By J. Saltz, P. Mehrotra
Papers awarded inside of this quantity hide quite a lot of themes concerning programming allotted reminiscence machines. disbursed reminiscence architectures, even supposing having the capability to provide the very excessive degrees of functionality required to help destiny computing wishes, current awkward programming difficulties. the most important factor is to layout equipment which allow compilers to generate effective disbursed reminiscence courses from rather computing device self reliant application necessities. This publication is the compilation of papers describing a variety of examine efforts aimed toward easing the duty of programming dispensed reminiscence machines
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Extra info for Languages, compilers, and run-time environments for distributed memory machines
Thus they can lead to efficiently executing programs even on machines where communication is expensive relative to computation. In order to do this, there must be enough computation available to hide the latency of the required inter-processor communications. Various optimizations also may be used to reduce the communication overhead. One optimization is to utilize the high degree of virtual parallelism to perform the computation for those virtual processors that do not require any off-processor communications while waiting for the required communications.
The latter two cases raise challenging problems with regard to contraction and load balancing. A related issue is that different phases of a complex algorithm may most naturally desire different mappings of the same data structure. One question this raises is how the language will support remapping of distributed data structures. This question is addressed in the recent FortranD proposal [9,15] and to a more limited extent in . A second question is how efficiently the compiler will be able to perform remappings.
For instance, the first two examples above are handled easily and naturally using this model. To be very broadly expressive, however, we feel it is also necessary to provide the possibility of explicitly designated sends and receives. In our current research we allow each concurrent process segment (composite procedure in DINO) to use either pseudo-SIMD or SPMD semantics, but not both, and we allow the parallel program to be composed of arbitrary combinations of these two types of composite procedures.